1. Field of the Invention
The present invention relates to a method for fabricating a multi-layer gate stack structure for a field-effect transistor (FET) device and to a multi-layer gate stack structure comprising a metal layer.
2. Background Information
Conventional integrated circuits comprise FET devices with an active area consisting of a source region, a drain region and a channel region between the source region and the drain region formed respectively in a semiconductor substrate beneath a substrate surface of the semiconductor substrate. Gate electrodes of the FET devices are formed above the channel region on a gate dielectric covering the substrate surface.
The gate electrodes of the FET devices are provided by first depositing a sequence of layers for a gate electrode layer stack on the gate dielectric and then patterning the gate electrode layer stack. In memory cell arrays the gate electrodes of a plurality of access transistors of memory cells form integrated constituent parts of gate tracks or wordlines for addressing the memory cells in the memory cell array. As the operating speed of the integrated circuits depends on the conductivity of the wordlines, materials with low resistivity are used for the gate electrode layer stack.
Efforts have been made to use a metal as one of the materials of the gate electrode layer stack. Usually tungsten is used for a metal layer in the gate electrode stack. As metal tends to diffuse into adjacent structures, thereby deteriorating, for example, the isolating properties of the adjacent structures, the metal layer is encapsulated at least towards the gate dielectric by a barrier layer suppressing the diffusion of metal. Adjacent to the gate dielectric, polysilicon is the preferred material, as the value of the work function best satisfies the requirements of the application.
In U.S. Pat. No. 6,198,144, a gate stack structure is described that comprises a polysilicon layer applied on a gate dielectric, an electrically conductive barrier layer applied on the polysilicon layer and a metal layer deposited on the barrier layer. The metal of the metal layer is tungsten and the barrier layer is made of tungsten nitride. On the metal layer, a silicon dioxide layer is deposited as an insulating cap oxide. A silicon nitride liner is provided on the sidewalls of the gate stack structure. When forming the tungsten nitride layer on the polysilicon layer, nitrogen is incorporated by the polysilicon of the polysilicon layer. Thereby a silicon nitride is formed deteriorating the electrical connection between the polysilicon layer and the barrier layer.
In German Patent Application DE 10 2004 004 864.9, an interface layer between the polysilicon layer and the barrier layer is described. The interface layer inhibits the incorporation of nitrogen in the underlying polysilicon layer. The interface layer comprises a refractory metal as, for example, titanium.
Another aspect of designing a gate stack structure is the height of the final gate stack structure. A reduction in gate stack height is desirable since process control deteriorates with increasing aspect ratio of the gate stack structures and of the trenches between them. Further, the source regions and the drain regions are formed by implants masked by the gate stack structures. To increase the performance of the access transistors of memory cells, angled implants adjusted by the upper edges of the gate stack structures are required. With increasing gate stack height, the range for the angle under which implants can be performed becomes narrower. Reducing the height of the metal layer would reduce the cross-sectional area thereof, leading to an unfavorable increase in the resistance of the wordline. The contribution of the barrier layer and the interface layer to the gate stack height is comparatively small.
The height of the polysilicon layer results from the process conditions of the etch steps performed during patterning the gate electrode layer stack. Patterning the metal layer, the barrier layer, the interface layer and the polysilicon layer in one step would require an etch that is effective on all materials of the stack and that does not damage the semiconductor substrate. Due to its thickness of about 2 nanometers for a typical gate stack structure width of less than 100 nanometers, the gate dielectric is not suitable to resist a longer overetch outside the gate stack structure.
Therefore the etch is commonly performed in at least two etch steps, wherein the first etch step is effective on the metal layer, the barrier layer and the interface layer and wherein the second etch step is effective on the polysilicon layer.
As a complete removal of the interface layer from the sidewalls of the gate stack structure must be secured, a first overetch into the underlying polysilicon layer is commonly provided.
The depth of the overetch into the polysilicon layer results from the condition to secure complete removal of the metal, barrier and interface layers respectively that are deposited consecutively as conformal layers on an uneven surface. In the vicinity of steps in the underlying surface a vertical thickness of the layers is increased, wherein the vertical thickness is effective for an anisotropic etch.
After the first etch step a dielectric passivation liner is usually formed that covers the sidewalls of the metal layer, the barrier layer and the interface layer being exposed by the first etch step. Opening the dielectric passivation liner before patterning the polysilicon layer requires a second overetch into the polysilicon layer.
The thickness of the polysilicon layer must be sufficient to permit the above-described overetches into the polysilicon layer.
Also the effect of divots between structures consisting of different materials in the underlying substrate surface must be taken into consideration. The material of the polysilicon layer fills the divots and the thickness of the polysilicon layer is locally increased, necessitating a further overetch of the polysilicon layer.
The various overetch conditions require a minimum process thickness of the polysilicon layer. The minimum process thickness is higher than a minimum functional thickness required by the electrical functionality of the polysilicon layer within the gate stack structure. A high gate stack structure is, however, not desirable for process technological reasons, in view of the quality of pattern and fill processes and in view of the range for an implant angle.